1. Field of the Invention
The present invention relates to a memory device. More particularly, the present invention relates to outputting compressed data of a memory device.
2. Description of the Related Art
Integrated circuit memory devices typically include one or more arrays of memory cells for storing data. Such memory devices include random access memories (RAM), dynamic random access memories (DRAM), Synchronous DRAM (SDRAM), static RAM (SRAM), and non-volatile memories such as FLASH.
During production of the memory devices, the individual memory cells need to be tested. In such a test, data is written into the memory cells, and then read out from the memory cells. As the density of the memory arrays increase, the test time of whole memory array test also increases.
One technique that is usually used to decrease test time is data compression. Data read from multiple memory cells are compressed into some particular data bits by a data compression circuitry included in the memory device. This compression technique allows parallel test for many memories and/or multiple array banks of a single memory, therefore shortening the testing time.
FIG. 1 is a schematic diagram from US Patent Application Publication No. 2007/0070740, which shows a conventional memory device with a compressed output data. In the memory test, the compressor 160 compresses the 16-bit data word read from the memory cell bank 120 into a single bit with a compression algorithm. The compressor 160 could hardly satisfy all the combinations of a 16-bit data word that are as many as 216=65,536. It is difficult for the compressor 160 to even satisfy a part of the 65,536 combinations to reach better fault coverage. Actually, to perform such read compression, each bit of the 16-bit data word must be written with the same data. Eventually, only 2 combinations are usually used, namely, the output data and its inverse.
FIG. 2 is a schematic diagram from U.S. Pat. No. 6,307,790, which shows another conventional memory device with compressed output data. The memory device in FIG. 2 has three data paths, depicted as A, B and C, respectively. Any one of the data paths A, B and C may be chosen to transmit the data read from the memory array banks 202a-202d to the output buffer 220.
When the data path A is chosen, one of the switches 212(a)-212(d) is turned on and the other switches are all turned off. The 16-bit data word read from one of the memory array banks 202a-202d is transmitted directly to the output buffer 220 without compression delay.
When the data path B is chosen, the switches 204(a)-204(d) and 207(a)-207(d) are turned on and the other switches are turned off. The 16-bit data word read from each of the memory array banks 202a-202d is compressed by one of the 4-to-1 compress logic circuits 206(a)-206(d) into a 4-bit data word. Obviously, the compression ratio is 4:1. The four 4-bit compressed data words are combined into a 16-bit data word and are transmitted to the output buffer 220. Since the original 16-bit data word is compressed into a 4-bit data word, the written data of 16-bit data word, where written data are data to be written into memory cells, has to be generated according to the 4-bit compressed data word. As a result, 24=16 possible values are generated for the 16-bit data word to be written.
When the data path C is chosen, the switches 204(a)-204(d) and 218 are turned on and the other switches are turned off. The 16-bit data word read from each of the memory array banks 202a-202d is compressed by one of the 4-to-1 compress logic circuits 206(a)-206(d) into a 4-bit data word. Each of the four 4-bit data word is further compressed by the 4-to-1 compress logic circuit 210 into a single bit. The compression ratio is 16:1. The four bits output by the 4-to-1 compress logic circuit 210 are transmitted to the output buffer 220. Since the original 16-bit data word is compressed into a single bit, the written data of 16-bit data word has to be generated according to the single bit. As a result, only 2 possible values are generated for the 16-bit data word to be written.